11/13/2020 0 Comments Odd Parity Checker
Empower Your Circuit Designing Skill with Virtual Lab, Today.Well, it might be a 0 or 1 in data transmission, depending on the type of Parity checker or generator (even or odd).But when we talk about the Parity Checker, its a combinational circuit that checks the parity in the receiver.
![]() Such a circuit can easily be implemented by using the Ex-OR gate ( as it gives 0 when the number of inputs is even). Let the 2 inputs A B are applied to the circuit and Y is the output bit parity. Now to génerate the even párity bit Y, thé total number óf 1s must be odd. The 2-bit message along with the parity bit is transmitted to the receiving end where the checker circuit checks for the error. The total numbér of 1s must be even in order to get the odd parity bit. The 2-bit data along with the parity bit is transmitted to the receiver where parity checker checks for the error in the message. ![]() Thus 3-bits are applied as the input to the parity checker where it will check for the possible errors. But if thé number of 1s counts to be odd then the received message contains an error. So in totaI, 3-bits are applied at the input of the Parity Checker. If the numbér of 1s at the receiving end counts to be even in number then an error has occurred. But if thé number 1s is odd then the transmission is taken as error-free. But along with these, there are few disadvantages also which are as follows. Data correction is not possible, so data has to be retransmitted. If that comes out to be odd, then the message is error-free else, at least one bit is corrupted. If that comes out to be even, then the message is error-free else, at least one bit is corrupted. IS there any way i can add up more bits on it, or double it more precisely. I want to get the high output if the data in the previous clocks have en even number of 1.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |